library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity corrimiento is
Port ( clk : in STD_LOGIC;
corrizq : in std_LOGIC;
corrder : in std_LOGIC;
G : in std_logic_vector (7 downto 0);
OEUPA : in std_logic;
YUPA: out std_logic_vector (7 downto 0));


end corrimiento;
architecture Behavioral of corrimiento is
constant s0 : std_logic := '0';


begin
process (clk,OEUPA,G,corrizq,corrder)
begin

if rising_edge (clk) then

			if OEUPA='0' 
				then YUPA <= "ZZZZZZZZ";
			end if;
				
			if OEUPA='0' and corrizq = '0' and corrder ='0'
				then YUPA <= G;
			end if;

			if OEUPA='0' and corrizq = '1' and corrder ='0'
						then YUPA <= G(6 downto 0) & s0;
			end if;

			if OEUPA='0' and corrizq = '0' and corrder ='1'
						then YUPA <= s0 & G(7 downto 1);
			end if;

			
end if;
end process;
end Behavioral;